HDL Core Lib News
HDL Core Lib
Wishbone b4 draft released
This new version includes a pipelined mode to cater for devices with high throughput and high latency such as DDR RAM chips. See the draft in Document.
HDL Core Lib
Wishbone slave core generator
Wishbone slave core generator (wbgen2) is a Lua script for generating VHDL Wishbone slave cores from a register set description provided by the user. By the ”slave core” we mean a HDL entity which is connected to Wishbone bus on one side, and on the other side it provides ports for accessing memory mapped registers, FIFOs and RAMs.