FMC TDC 1ns 5cha News
FMC TDC 1ns 5cha
02-02-2012: V2 design ready
Based on the experience with the V1 prototype, nine
Issues were found.
Corrections have been made to the schematics and PCB layout and these
will be reviewed on 7 February. After this CERN’s design office will
generate the final production files.
The firmware VHDL code is under thorough review and production test
software has to be written. This work should be ready by the end of the
summer.
FMC TDC 1ns 5cha
30-05-2011: 3 prototypes assembled
Three prototypes of the Time to Digital converter have been built. We made a start of the VHDL coding for use on the SPEC PCI Express FMC carrier.
FMC TDC 1ns 5cha
18-03-2011: Schematics design review held
After a first global schematics review in the week before, a second schematics design review was held with five engineers who found a few details that will improve the functioning and the documentation of the schematics. The PCB layout will likely start in a week’s time.