EtherBone Core News
EtherBone Core
Etherbone Hardware Master
Finished the first hand tested version of a hardware eb master recently. So far everything works nicely and it looks quite performant, the interface looks and feels a bit like a DMA controller kind of thing.
EtherBone Core
Transparent Bridge Wrapper for EBM
A transparent bridge approach over UDP should be feasible, but there are restrictions for this usecase. These would be: - Only one packet in flight at any given time to avoid reordering
EtherBone Core
EtherBone goes BETA
As shown at the WhiteRabbit Workshop, we now have running Hard- and Software implementations. The EtherBone HDL core provides a slave module to go with the WR PTP core, while the API is flexible in its role and platform independent.
EtherBone Core
Initial EB master slave on hardware: the aftermath
I did a little dry run implementation sending back and forth messages in inside one FPGA for the last WR Dev workshop, reading and writing and reading data to and from a PWM controller hooked up to some LEDs.
EtherBone Core
Etherbone Dissector for Wireshark
I’ve written this a while ago to inspect the EB packets generated from my testbenches and test for conformity. This is for the not yet exisiting version 0.2, so it will need some work from Wesley
EtherBone Core
version from workshop demo uploaded
-Repo file clean up and renaming done -Serialiser/Deserialiser to/from std_logic_vector implemented as top_level EB_CORE_std_lgc_vec.vhd TODO: - cleanup code according to style guide - rename signals with new nomenclature - minor performance improvements
EtherBone Core
Etherbone/FEC demo layout
FEC is a complete standalone encoder/decoder block which can be bypassed Etherbone core will only support Wishbone slaves, not masters. Remote EB Mastre will be in software on intel based PC with a GUI