The aim of the board is to improve the jitter performance of the 10 MHz and PPS outputs of WR Switch using an external PLL and a new VCTCXO. This project is a spin-off of the general WR low jitter project.

The board needs to be mounted inside an existing WR-S3/18 switch, on top of the Switch Control Board (SCB) and will use the installed 12V power supply of the WRS. It needs a new external 10 MHz input, to be used instead of the current 10 MHz input when configured as Grand Master. The improvements are also effective when configured as boundary switch, thanks to the new VCTCXO.

The proposed board can be installed in any PCB v3.3 and v3.4 versions of the switch.

Key results about the perfomance improvement are published in M. Rizzi, et al. White Rabbit Clock Synchronization: Ultimate Limits on Close-In Phase Noise and Short-Term Stability Due to FPGA Implementation in IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control, vol. 65, no. 9, pp. 1726-1737, Sept. 2018. doi: 10.1109/TUFFC.2018.2851842

Image of the Low-Jitter Daughterboard

Contact