Resource Evaluation of WR switch HDL for Ultrascale Plus
The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA (MPSoC XCZU11EG-1FFVC1156E).
The aim of this project is to evaluate resources required to run wr switch HDL on Xilinx Ultrascale+ FPGA (MPSoC XCZU11EG-1FFVC1156E).