High Energy Physics applications require that a RF signal source is distributed along the accelerator chain and its detectors. Current implementations make use of dedicated links to transport the reference signal with minimal jitter and latency. With the arrival of the White Rabbit, which distributes timing over an Ethernet with sub nanosecond accuracy and picosecond jitter, other solutions to distribute the RF reference emerged.
Instead of using dedicated link to transport the RF reference, the Distributed RF over White Rabbit (WR-DRF) project aims to distribute a RF reference in a network where data, timing and the RF reference share the same link. The project aims to achieve similar performance as the current dedicated links, but in a more flexible and cost effective solution.
Current solutions to distribute the RF signals require high network bandwidth, thus the reason to use dedicated links. The proposed system architecture realizes a set of digital signal processing manoeuvres on the RF signal so that only its phase variation is transmitted which uses a relative low network bandwidth. This technique is only possible to be implemented due to the tight frequency and phase synchronization between the WR nodes, in addition to its fixed packet latency.

At the transmitter side, the RF reference signal is sampled with Bandpass sampling that allows the digitalization of RF signal at relative low frequency. Theoretically in the bandpass sampling technique the ADC is capable of digitizing a high frequency signal such that its sampling frequency is two times the bandwidth of the continous signal. An associated problem of this technique is the effects of aperture jitter. Jitter degrades the frequency at which the sampling occurs and thus degrades the performance of the technique. Nonetheless, this problem can be mitigated.
In addition this technique allows true flexibility on the type of RF signal as the sampling frequency of the ADC can be easily reconfigurable.

The digitized RF signal is down converted and processed in a configurable integrated circuit, for low cost and flexibility of the design.
The sampled RF signal is down converted to (Fc-Fs) where Fc is the RF carrier frequency and Fs is the ADC sampling frequency.
Although the RF signal has been digitally downconverted using the bandpass sampling technique, the transmission of the digitized signal still requires a bandwidth equal to the sampling frequency. For instance, if the sampling frequency is 100 MHz, the bandwidth required to transmit the digital signal trough the network would be 800 MBPS assuming a 8 bit resolution which is 64% of the network bandwidth, a non practical solution.

In order to reduce the bandwidth required to transmit the bandpass signal over the link an IQ transformation is applied to the signal so that only the necessary bandwidth to represent the digitized signal is effectively used in the transmission. The IQ demodulation is efficiently implemented in a reconfigurable integrated circuit with the CORDIC arithmetic. The CORDIC allows the computation of the sine and cosine recursively using simple shift and add operations and a relative small memory block containing arctan(2^i). The accuracy of the CORDIC is sensitive to the number of recursions and the number of bits in the calculation of its parameters. Due to the fact that CORDIC is a recursively algorithm it adds extra latency to the system.

Low pass filtering is required to remove the RF artifacts generated by the IQ processing. Finally, decimation is processed on the IQ signal to remove unnecessary data required to build the modulated signal. Typically at least two times the bandwidth of the system is required to transmit the IQ signals. For instance, if the bandwidth of the RF signal is 2 MHz then at least 4 MHz is required to transmit each IQ signal, this means 32 MBPS, a more efficient system.
This method, typical used in baseband communications, just requires the transmission of the change in amplitude and phase of the RF signal. Typically the bandwidth of HEP RF sources is around 1 MHz.

At the receiver side, the IQ information is extracted from the Ethernet packets. The data is then interpolated to reconstruct the IQ data, that is up convert the data to have the transmitter sampling data, Fs. The IQ data is digital mixed using the same frequency and process realized in the transmitter side. After the mixing both resulting signals are summed up to obtained a copy of the digital clock signal sampled by ADC in the transmitter side.

A DDS system, implemented in the FPGA, is used to upconvert the signal to its carrier-modulated. The implementation of a DDS system enables the generation of not just the carrier-modulated frequency but also other frequencies with high frequency resolution. Another advantage is the frequency agility that is the change of the clock frequency with virtually no settling time. In addition the DDS adds a high level of phase resolution. In applications where a broad spectral purity is required then a use of a PLL to upconvert the bandpass signal is necessary.

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