In wbgen2 terminology, a ”slave core” is an HDL entity which is connected to Wishbone bus on one side, and on the other side it provides ports for accessing memory mapped registers, FIFOs and RAMs, as shown on the following figure:

wbgen2 simplifies creation of such cores, by automatically generating HDL code, C code and documentation from a single, easily editable file.

Features supported by the latest version:*

• Customisable register types, with multiple access options and multiple clocking schemes
• Configurable memory blocks
• Peripheral-level interrupts via Embedded Interrupt Controller
• Generation of VHDL/Verilog synthesizable code
• Automatic address space layout generation
• Generation of C header files containing memory map consistent with the HDL core
• Support for popular synthesizable VHDL data types

Foreseen in near future*

• FIFO register support
• Pipelined Wishbone support

The primitives are accessible from outside the slave core as VHDL/Verilog signals:

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