This wiki page describes the PCI-Express to VME bridge HDL module. It was originally implemented by MEN Mikro Elektronik GmbH on the A25 SBC and later open-sourced in the context of the CERN’s VME Single Board Computers supply contract.

The PCIe-to-VME bridge translates the read and write operations in the PCIe address space to read and write transactions on the VME bus. It acts as a PCIe Endpoint on one side and VME bus Master on the other. The bridge can generate VME single cycles and block transfers. The following access types are currently supported:

• VME single cycles: A16, A24, A32 with any of the D8, D16, D32 data widths
• VME block transfers: A16, A24, A32 with any of the D8, D16, D32 plus the A32D64 multiplexed block transfer (MBLT)

The VME block transfers are executed by a built-in Direct Memory Access (DMA) engine, where the blocks of data are transferred between the system memory and the VME bus, bypassing the CPU. In general this is a faster and more efficient way of exchanging multiple data words, as the CPU is free to continue its normal operation until the DMA engine is done with a programmed task. The bridge supports also some features added in the VME64x extensions. It is able to use the geographical addressing pins and generate a special type of A24 access to read and write the CR/CSR configuration space of VME slaves installed in the same crate. However, none of the fast transfer modes (2eVME, 2eSST) is currently implemented.

If you’re looking for a VME-bus Slave, see the project VME64x to Wishbone Core.

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