TDC core
The TDC core is a high precision (sub-nanosecond) time to digital conversion core for Xilinx Spartan-6 FPGAs.
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First test results
The test report of the time to digital converter (TDC) core is available in the documents section: https://www.ohwr.org/project/tdc-core/wikis/Documents/Test-report.
Preliminary design of the data path done
The basic data path of the time to digital converter (TDC) core is now designed. It consists of delay line based on a tapped carry chain, encoder (both leading + falling edges of the input signal are reported) and LUT (dual-port block RAM that serves to translate the raw encoded output of the delay line to a calibrated fixed point value).