The idea of a self-description for a bus appeared while working on White Rabbit and related projects that make massive use of FPGA devices. Separately and concurrently, both the CERN and the GSI working groups identified the need for some way to self-detect the contents of a specific logic device after it is programmed. We envisioned that if the internal FPGA bus could enumerate its own content, we would get a lot of advantages.

As usual in engineering, we wanted a system that was as simple as possible, yet open to future extensions without introducing compatibility issues. While our internal bus is Wishbone, we designed the structures to be generic so other
bus implementations may use them.

The Self Description Bus allows to enumerate the cores that are live in the current fpga binary, either from the host computer or from the internal soft-core CPU in the FPGA itself. It is also used as a simple filesystem in our EEPROM devices, so data can be easily accessed by both the host and the soft core that lives in the FPGA itself.

The current specification is already in use in some of our designs.

Contact