QDR II controller for Virtex 6
This core is a QDRII controller with two pipelined Wishbone slave
ports.
It is based on the Virtex-6 hardware core and a management core for
QDRII+ generated by Xilinx
CoreGen.
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QDRII memory controller core
The prototype of the QDRII controller is based on the Switch Core Board version 3 (SCBv3) developed by Seven Solutions. The ongoing work of this memory controller is available in the SVN repository.