VHDL macro libraries for Microsemi ProASIC3
This is a collection of simple macro implementations for Microsemi’s FPGAs to allow simulating post-synthesis designs using GHDL.
These have been originally designed to target the ProASIC3 families but they should also work just fine for the Igloo, SmartFusion and Fusion as per Microsemi’s documentation.
The original macro collection has been created by Yann Guidon and posted as a hackaday.io project. It has then been expanded and posted in the form of this OHWR project with permission from the original author. One feature that has been added and stands out is the capability of (optionally) injecting bit-flips in the registers of a design to test TMR’ed implementations in post-synthesis simulations with GHDL.