Following the evaluation of different implementation solutions, the technical choice for the design was the use of Mock Turtle (also referred to as White Rabbit Node Core).

Mock Turtle is a HDL core of a generic distributed control system node, based on multiple deterministic CPU cores where the users can run any sort of hard real time applications.
The applications can be written in bare metal C, using standard GNU tool set, cross-compiled and loaded into the CPUs. The CPUs can communicate between each other through
a dedicated Shared Memory and with the host through Host Message Queues.The following figure illustrates the SPEC FPGA gateware architecture, spec_masterfip_mt.

Overview of the gateware architecture of the fmc-masterfip on a SPEC carrier*

The top entity consists of two main blocks: the spec_node_template*, which is the Mock Turtle top level for SPEC, and the application-specific fmc-masterFIP_core.
The communication between the two modules is through wishbone.

On one side (red arrows) the fmc_masterfip_core is the interface to the FMC hardware i.e. FielDrive chip, external pulse LEMO, 1-wire DS18B20 chip, LEDs.
On the other side (blue line) it provides a set of wbgen2 -generated control and status registers, to interface through wishbone with the Mock Turtle.

The fmc_masterfip_core core ignores the notion of the WorldFIP frame type (ID_DAT/RT_DAT/..etc), or the macrocycle sequence and macrocycle timing; the sw running on the
Mock Turtle CPUs is responsible for managing these aspects and for providing to this core all the payload bytes (coming from the host) that have to be serializedand or
for enabling the deserializer and then providing to the host the deserialized bytes.

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