The LRFSC card takes an analog signal from a pickup in a Radio Frequency accelerating cavity, compares that signal with a set point and drives an amplifier to correct the field in the cavity. It implements a digital feedback system in an FPGA which is at the heart of a VME32 board. This project is not meant to be the basis of any new developments. The FPGA used (Xilinx Virtex 2) is not commercially available any more. Links to useful information:

• EDMS page at CERN, containing the schematics, layout, BOM and other useful documents.
• The Documents tab of this OHR project, containing a couple of write-ups about the software.
• The repository in this OHR project, containing the VHDL sources for the FPGA.
• Publications:
  • All Digital IQ Servo-System for CERN Linacs, PAC 2003.
  • All Digital IQ Servo-system for CERN Linacs, EPAC 2004.
  • FPGA-based Low Level Control of CERN’s LINAC 3 Cavities, ICALEPCS 2005.

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