HDL Core Lib
The Corelib project covers the development of re-usable HDL cores for FPGAs, each of which is a separate sub-project (see complete list).
Although there are no strict rules on practices, there is an emerging coherency developing around the concept of Wishbone-based design. We collaborated in the update of the Document to include a pipelined mode which enhances communication with high-latency high-throughput devices, such as DDR RAM controllers.
Another important development is the Wishbone slave generator, which helps in the repetitive task of creating Wishbone slaves in VHDL and Verilog.
Rules & Policies:*
- For VHDL development, please use the Document.
- For the rules of using the Git repos, see HDL-Git-Rules
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Latest News
Wishbone b4 draft released
This new version includes a pipelined mode to cater for devices with high throughput and high latency such as DDR RAM chips. See the draft in Document.
Wishbone slave core generator
Wishbone slave core generator (wbgen2) is a Lua script for generating VHDL Wishbone slave cores from a register set description provided by the user. By the ”slave core” we mean a HDL entity which is connected to Wishbone bus on one side, and on the other side it provides ports for accessing memory mapped registers, FIFOs and RAMs.