FMC PCIe Carrier PFC

This project is cancelled. The simple PCIe FMC carrier is similar.

The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an SFP connector. On the PCIe side it has a 4-lane interface, while the FMC mezzanine slot uses a low-pin count connector. In fact it uses a high-pin count one, but apart from a single clock signal and 4 Gigabit links only the low-pin count part is wired. Also some additional, non-standard power supplies are provided on the high-pin count part of the connector.

A big stress has been put in the versatility of the clocking resources, making this card an ideal component of a synchronous distributed system.

Other FMC projects and the FMC standard are described in FMC Projects.

First prototype large

Main Features*

  • 4-lane PCIe bus (Gennum GN4124)
  • FMC slot
    • 1 full LPC slot
    • DP1 to DP4 gigabit links of HPC
    • CLK2_BIDIR and CLK3_BIDIR only from carrier to mezzanine
    • +5V, -2V, -5V2 and -12V optionally wired on HPC pins
  • 1 Spartan6 FPGA, XC6SLX150T-2FGG676C
  • Flexible clocking resources
    • 2 Voltage Controlled Temperature Compensated Crystal Oscillator (VCTCXO)
    • 1 any rate I2C programmable crystal oscillator (Si570)
    • 1 Direct Digital Synthesizer (DDS) (AD9910)
    • 2 Phase Locked Loop (PLL) chips for clock cleaning and redistribution to the FPGAs and the pluggable modules (AD9516-4)
  • On board memory
    • 72Mbit QDR-II SRAM (CY7C1512KV18-250BZXC)
    • A 2Gbit DDR3 (MT41J128M16HA-15E)
    • 1 SPI 128Mbit flash proms for multiboot FPGA powerup configuration, storage of the FPGA firmware or of critical data
  • Front panel connectivity
    • Small Formfactor Pluggable (SFP) fibre-optic connector
  • Internal connectors
    • 2 e-SATA connected to 2 GTP blocks
    • 1 e-SATA connected to 1 AD9516-4 LVDS output and 1 FPGA differential IO.
    • 1 e-SATA connected to a AD9516-4 CLK_IN and to an FPGA GCLK, and 1 FPGA differential IO.
    • 1 JTAG header
  • FPGA configuration. The FPGA can optionally be programmed from:
    • JTAG header
    • GN4124 GPIO
    • SPI EEPROM or GN4124 SPRIO interface (selected with optional 0Ohm resistors)
  • 12-layer PCB
  • White Rabbit will be supported by the FMC Standard Kit carriers.

Contact

Javier Serrano

Latest News

28-02-2011: CERN's PFC card on Gennum's blog

CERN’s PFC card and the Gennum to Wishbone core is featured on Gennum’s GN4124 Design blog

03-02-2011: First DMA transfer to/from DDR3

A first DMA transfer to the PFC DDR3 and back to the host has been done this morning. The DDR3 interface seems to work well, but more exhaustive test of the DDR3 interface are still to be done.

10-12-2010: PCIe communication to Wishbone registers working

The communication chain of writing and reading Wishbone registers inside the Xilinx via the Gennum PCIe bus interface is working.