On the “repository” section: https://www.ohwr.org/project/fmc-delay-1ns-8cha-sa/tree/master we offer a new framework able to provide stand-alone operation of SPEC-based nodes (SPECv4/SPEC100 carriers), although it is easily portable to other ones. As demonstration FMC DEL stand-alone mode has been implemented. FMC DEL driver code is used to produce a firmware. This binary runs on an embedded LM32 processor (OS calls and libraries has been substituted keeping their original interfaces). It is responsible for the initialization of the ASICs integrated on the mezzanine including output delay lines calibration and calibration values update.

This new framework can be used as an on-board programmer to load a new firmware on LM32-based cores, on-board debugger/tester able to perform and supervise user-programmed signals/registers tests and execute commands send through Etherbone.

The FMC Delay 1ns-4cha is an FPGA Mezzanine Card (FMC – VITA 57 standard), whose main purpose is to produce pulses delayed by a user-programmed value with respect to the input trigger pulse. The card can also work as a Time to Digital converter (TDC) or as a programmable pulse generator triggering at a given TAI time. It is implemented using a dedicated time-to-digital converter ASIC, TDC-GPX, from the European company Acam.

A FMC Delay mezzanine has to be integrated with a carrier (FMC/SPEC or FMC/SVEC) and needs to go through a complex initialization process. This process includes: starting some built-in on-chip bus and IO controllers, programming the PLL contained on the mezzanine and calibrating the output stages. Output stages calibration is performed (using ACAM’s TDC-GPX chip) in order to ensure that the delay introduced is consistent with the programmed settings minimizing jitter. In addition to that, to compensate temperature effects the calibration values must be updated periodically.

When the node is plugged on a PC, the driver (through PCI/Gennum) is entrusted with this task and therefore, a node incorporating this mezzanine could not be operated as a stand-alone one. The software and gateware developed allow for stand-alone operation of FMC Delay + SPEC node. The code runs on the embedded LM32 processor that initializes, calibrates and periodically adjusts the calibration values and also provide two mechanisms (local, via RS232 and remote, using CALoE) that permit users to work with a FMC Delay on-SPEC node as when plugged on a PC. The lack of the support from the O.S. is overcome with new software that properly substitutes fmc-bus and spec driver while the compatibility with the FMC Delay driver is assured. That way functionality and programming interfaces are preserved.

Fig 1. FMC Delay on-SPEC node gateware block diagram.

The gateware architecture is illustrated in figure 1. The GN4124 core has been replaced for a new soft-procesor core that includes RS232 support for configuration/programming purposes and a UART selector that allows to choose between this internal UART or an external one. Regarding the software, as the pair OS/driver is not present, functions and functionalities provided by SPEC and FMC drivers, ZIO as well as the libraries from the Linux headers (that are still needed) had been reimplemented but keeping their interface. As the design is intended to be driver- compatible, both, interface and function implementations have been re-utilized (which means that the API is preserved).

The target is a fully operational stand-alone FMC Delay based White-Rabbit node which can be initialized and perform periodic calibrations without requiring to be plugged on a PC, reducing final system cost, size and power consumption.

Fig 2. Soft-Micro Debugger block diagram.

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