The fmc-adc-subsamp125m14b4cha is a 4 channel 125MSPS 14 bit ADC low pin count FPGA Mezzanine Card (VITA 57). It was designed within the framework of the WR-D3S-ADC project to bandpass sampling signals with a carrier frequency higher than 125 MHz, but BW of only a few MHz. The design was based on the fmc-adc-100m14b4cha, but two main changes were applied:

- the ADC LTC2174 was replaced with the pin compatible LTC2175 in order to increase the sampling frequency to 125MHz and synchronize it using the WR clock.
- the input acquisition circuitry of every adc channel was simplified and replaced by RF transformers as recommended into the ADC datasheet.

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