FPGA and ARM SoC FMC Carrier FASEC
This card is a carrier for two low pin count FPGA Mezzanine Cards (VITA
57) with additional 200 kSPS bipolar analog inputs, Ethernet
connectivity and fail-safe functionality.
The card has been developed within CERN’s TE-ABT
group
for the Fast Interlocks Detection System (FIDS) project.
The main controller is a System-on-a-Chip from Xilinx, the Zynq XCZ030 that consists of two silicon ARM cores and FPGA fabric. The idea is to implement fast interlocking logic (<100ns reaction time, 1 ns resolution measurements) in the FPGA while the processor, running Embedded GNU/Linux, runs user applications to control deterministically the equipment and communicate with other devices and CERN’s Controls MiddleWare (CMW). Additionally there is DDR3L memory, clocking resources and support for the White Rabbit timing and control network. Stand-alone board for use in a 19" rack 1U crate (aka pizza-box).
Recent RFoWR fork of this project at https://ohwr.org/project/city/wikis/home