DDR3 controller for Spartan6
This core is a DDR3 controller with two pipelined Wishbone slave
ports.
It is based on the Spartan6 hardware core and a management core
generated by Xilinx
CoreGen.
Contact
Licences
Latest News
New release
version#126 is now available with tag “1.0” in the repository.
First prototype of the core available
The prototype of the DDR3 controller is based on the SP605 development kit from Xilinx. It is available in the SVn repository.