WR Switch firmware v4.2 released

After some months of hard work we’re happy to announce a brand new v4.2 stable firmware release for the WR Switch. It is full of new features and stability improvements. As usual, you can find all the links to download the firmware binaries and manuals on our release wiki page.

Main features on the software side include:

  • improved boot scripts - now you can manually start/stop services using /etc/init.d/* scripts
  • Monit to supervise running processes and restart them if they crash
  • reorganized and improved SNMP monitoring - you can find there raw expert values as well as the general status information about your switch
  • dot-config configuration file which can be fetched on run-time from a central server using tftp/ftp/http protocols
  • temperature monitoring inside the WRS box and rising an alarm if it’s too high
  • improved root password handling - now you can configure it in clear text or encrypted in the dot-config file
  • setting system time from the WR time (in Slave mode) - to have consistent logs from all the switches in a network
  • improved LED signalization on the front panel
  • reorganized and cleaned up internal software libraries
  • lowered CPU usage by exporting information from various daemons using SHM instead of IPC calls
  • fixed bugs since the last release
  • cleaned up the code

Main features on the gateware side include:

  • generation of the WR-synchronized 10MHz aux clock - only in v3.4 hardware
  • performed serious stress tests and provided many fixes in the HDL modules responsible for Ethernet switching - WRS does not crash anymore under a high load of traffic
  • fixed resetting Xilinx FIFOs in the Endpoints - was causing sometimes a random port to stall forever after powering up the switch
  • SDB support to export information about the Wishbone modules and synthesis information (metadata) - software still does not use the SDB data, this will come with v4.3 release
  • HDL watchdog module for monitoring the Switching Core operation - in case there is still some not-yet-explored bug which could freeze the whole switch
  • modified PSTATs module to improve timing closure for the 18-ports synthesis
  • bugfixes and code clean-up

You can find a list of the main features and bugfixes in the roadmap table for two subprojects:

Thank you for all the bug reports and contributions. As always, we encourage you to try this fresh release on your switches.