We are happy to announce the new v3.0 stable release of the WR PTP Core. It comes with new features and stability improvements. As usual, you can find all the links to download the binaries, sources and manuals on our release wiki page.

This new release includes:

• fixes for synchronization when high load of non-PTP traffic goes in the background
• fixes to withstand heavy Ethernet traffic - the result of WR Switch testing and debugging done for v4.2 firmware release
• locking helper PLL below the reference frequency - which solves the DAC range problem on the SPEC board
• Flash and SDBFS support for storage
• Kintex-7 support - very nice work (including fixes for various well hidden bugs that we did not observe on SPEC) done by Peter Jansweijer
• TX runt frames padding - another kind contribution from Peter to be compliant with IEEE802.3 standard
• increased size of the LM32 RAM (now it is 128kB)

Please be aware, that this release by default uses SDBFS for storage. This means, you have to write the SDBFS image to Flash/EEPROM before using the core. Please check the FAQ and the release documentation for more information on how this should be done.
In the future, writing SDBFS structure to Flash should be done by manufacturers of hardware to assign official MAC addresses like they already do for WR Switches.

You can find a summarized list of the main features and bugfixes on the WRPC wiki page and a little bit more detailed information in the roadmap for two subprojects:

• WR PTP Core gateware roadmap
• WR PTP Core software roadmap

Thank you for all the bug reports and contributions. As always, we encourage you to try this fresh release on your boards.