The basic data path of the time to digital converter (TDC) core is now designed. It consists of delay line based on a tapped carry chain, encoder (both leading + falling edges of the input signal are reported) and LUT (dual-port block RAM that serves to translate the raw encoded output of the delay line to a calibrated fixed point value).

Timing is easily met for a 125MHz clock in the XC6SLX45T device in the slowest speed grade (-2), with a total of 5 cycles of latency (40ns) and a 400-tap delay line. According to the Xilinx timing model, the signal takes 12.069ns (10.035ns in -3 speed grade) to reach the end of the delay line. This should give a good margin above the 8ns of the 125MHz clock.

Since this part is the critical component of the TDC, these results support the feasibility of the design.