Layout has taken a bit longer than anticipated, however the end is now in sight! Supporting dual FMC-LPC connectors, DDR3 memory and various other high speed signals, placed some stringent impedance and length matching rules on many of the nets from the FPGA. As a result, the layout process was somewhat challenging. We ended up with 14 layers to accomodate all the constrained signal-ended and differential nets. For those interested we have placed an image of the Altium 3D CAD model for Rhino on the project wiki page.