News

nanoFIP Test Board

22-03-2010: Schematics ready for review

The schematics and documentation are ready for the review that will be held on 26 March.

FMC ADC 100M 14b 4cha

19-03-2010 PCB layout done. Review planned

PCB review planned for 24 March 2010.

White Rabbit

MCH v2 working

Version 2 of the White Rabbit switch uplink port card is back from production. Tomek has successfully tested two units and he will now proceed to organize the production of ~10 more.

FMC DIO 16ch TTL a

5-03-2010 Digital I/O card working

The 16-channel digital I/O card is working. The driving logic is implemented as Wishbone registers that are created using the Wishbone slave core generator. Only simple, static tests with a simple wishbone master have been made.

FMC ADC 100M 14b 4cha

2-03-2010 Schematics review held

The schematics review (Review02032010) revealed some serious problems and signalled other issues that will make the design more robust. Other comments will make that the documentation will be improved. The changes will be implemented before finalising the PCB layout.

FMC DIO 16ch TTL a

2-03-2010 First FMC prototypes

Two fully assembled (including optional test connectors and LEDs) digital IO FMC prototypes are available. See more here. Tests with a Spartan6 development kit will start soon!

OHR Support

White Rabbit and FMC kit presented in Berkeley Lab

The White Rabbit network was presented in UC Berkeley to the Ptides team in the EECS Department on 25 February. Another presentation (see slides) was held the next day in Berkeley Lab, with members of the ALS team.

HDL Core Lib

Wishbone slave core generator

Wishbone slave core generator (wbgen2) is a Lua script for generating VHDL Wishbone slave cores from a register set description provided by the user. By the ”slave core” we mean a HDL entity which is connected to Wishbone bus on one side, and on the other side it provides ports for accessing memory mapped registers, FIFOs and RAMs.

FMC ADC 100M 14b 4cha

24-02-2010 Draft PCB layout done. Review planned

Draft PCB layout done. Design document being written. Design review planned for 2 March. See documents here.