News
nanoFIP Test Board
28-09-2010: Production and consumption of variables working
The production and consumption of variables is working and has been tested for over two days. The data is not yet checked continuously, we’re waiting for an extension of the firmware of the NanoFIP test board that allows the NanoFIP to resend the data it has received.
RHINO
RHINO Project Page update
Added information to the wiki page Uploaded the Rhino block diagram and schematics
FMC PCIe Carrier PFC - Software
uploaded current status of FMC Carrier software
The current release includes a raw I/O driver, used in developing the VHDL code for the carrier. I uploaded the tarball (it’s git internally) and the pdf document – which is in the tarball as well.
Conv TTL NIM 3in 30out
22-09-2010: Start production of prototypes
The layout of the TTL to NIM converter board is ready and the production of 3 prototypes has been launched.
FMC PCIe Carrier PFC
23-09-2010: Front-panel ordered
The PCIe front-panel with the cut-out for the FMC front (and fibre-optic connector) has been ordered. It will be a one-piece design. Another, more conventional 3-piece design will also be ordered soon.
White Rabbit
First two-month development cycle for WR switch started
The WR switch design effort is transitioning into a new development model, with two-month cycles that include a kick-off meeting for planning the two months of work and a meeting at the end to check results.
FMC PCIe Carrier PFC
16-09-2010: Requested production of PCBs.
The PCB layout of the FMC PCIe carrier has been finalised and the production of four PCBs has been requested. Three of them will be assembled and one will be kept empty for being able to measure for connectivity, if needed.
VXS DSP FMC carrier
13-09-2010: OHR Wiki page started
The VXS DSP FMC carrier design, to be developed by the BE-RF-CS section at CERN will take part in the Open Hardware project. A Wiki page has been made including a block diagram.
Simple PCIe FMC carrier SPEC
10-09-2010: PCB layout start
The comments from the schematics review have been taken into account and PCB layout starts. The aim is to make a low cost 6-layer board (cf. a 12-layer one for the more complex FMC PCIe Carrier - PFC), while paying much attention to signal quality issues such as signals crossing splits in the power planes.