News
OHR Meta Project
08-07-2011: CERN releases Open Hardware License v1.1
“Four months after launching the alpha version, CERN has today issued version 1.1 of the Open Hardware Licence (OHL), a legal framework to facilitate knowledge exchange across the electronic design community.
CernFIP
08-07-2011: nanoFIP reprograms Xilinx & Actel FPGAs
We are moving towards the completion of the nanoFIP JTAG controller feature! nanoFIP is now able to receive WorldFIP frames that are translated into JTAG instructions for the reprogramming of other FPGAs.
OHR Meta Project
Open Hardware workshop to happen in October
We are preparing an Open Hardware workshop to discuss legal aspects, commercial models, tools and designs. More info here.
OHR Support
OHWR maintenance on 2011-07-07 morning (Thursday)
added by Enrique GarcÃa on 2011-07-04 09:49:36.414749 Hello everyone, The ohwr site will be under maintenance next Thursday morning. The update will start at 8:30 CET and will likely take less than 30 minutes to complete.
Simple PCIe FMC carrier SPEC
01-07-2011: V2 boards tested
Three V2 boards have been received. One has already passed the full production suite, two others have only received a very short test (and passed). This means that this version can be used to start a series production.
OHR Support
OHWR maintenance on 2011-06-27 morning (Monday)
added by Enrique GarcÃa on 2011-06-24 09:47:33.863354 Hello everyone, The ohwr site will be under maintenance next Friday morning. On this update, we’ll be updating the site to a new Redmine codebase (Chiliproject) as well as adding a plugin to manage web robots, such as google.
VME FMC Carrier VFC
17-06-2011: Sprinting bears fruit: 14 issues found
Since the Scrum sprint to quickly debug the design with four engineers, already fourteen hardware problems have been found. Many are small bugs, but it also has been found that the SFP serial inputs are not usable as the Tx and Rx part are swapped.
CernFIP
17-06-2011: Start-up of JTAG developments
In collaboration with Stephen Page (TE-EPC) we are working on the JTAG extension of the nanoFIP chip! This extension will give to the user the possibility of reprogramming another FPGA through WorldFIP.
VME FMC Carrier VFC
07-06-2011: Sprint to debug fast
As the project is going slower than we want, we decided to start a sprint to debug the hardware design. For two to three weeks four engineers will be intensively working on testing and debugging the design.