The design of the nanoFIP chip is working. Tests are progressing very smoothly thanks to the extensive simulation models written by G. Penacoba. The actual hardware is tested on the NanoFIP test board that talks to other equipment in CERN’s WorldFIP laboratory that is run by J. Palluel. While the VHDL code is being optimised the tests are on-going. Soon a VHDL code review will be held.